GPIOs 4 and 5 are the only ones that are always high impedance. All others do have internal pull-ups or are even driven low/high during boot.
GPIOs 3, 12, 13 and 14 pulled HIGH during boot. Their actual state does not influence the boot process.
GPIOs 0, 1, 2 and 15 are pulled HIGH during boot and also driven LOW for short periods.
The device will not boot if 0, 1 or 2 is driven LOW during start-up.
GPIO 16 is driven HIGH during boot, don't short to GND. 


http://rabbithole.wwwdotorg.org/2017/03/28/esp8266-gpio.html

GPIO Behaviour Summary
D0 	16 	High 	High during boot, falls after ~110ms (to ~1V?) 	High during boot, falls after ~110ms (to ~1V)
D1 	5 	Low 	Low 	Low
D2 	4 	Low 	Low 	Low
D3 	0 	Low then oscillates 	Varies, stabilizes high after ~100ms 	Varies, stabilizes low after ~110ms
D4 	2 	Varies, stabilizes high after ~60ms 	Varies, stabilizes high after ~70ms 	Varies, stabilizes low after ~110ms
D5 	14 	High 	High, then low after ~110ms 	High, then low after ~110ms
D6 	12 	High 	High, then low after ~110ms 	High, then low after ~110ms
D7 	13 	High 	High, then low after ~110ms 	High, then low after ~110ms
D8 	15 	Low 	Low, with glitch ~110ms 	Low, with glitch ~110ms
D9 	3 	Low 	Low until ~50ms then high 	Low until ~50ms then high until ~110ms then low
D10 	1 	Low 	Low until ~50ms then high 	Low until ~50ms then high until ~110ms then low

Conclusion: GPIOs D1 and D2 are the only safe GPIOs I can use to drive relays if I don’t want them to operate autonomously at boot. I will have to rework my PCB:-(

D3, D4 dürfen während dem boot nicht auf low gezogen werden, sonst bootet der ESP nicht -> nicht als Eingang zu gebrauchen, außer für Taster die während des bootens 
ziemlich sicher nicht betätigt werden. 


Daher folgende Pin-Zuordnung:
D1/GPIO5 -> power switch
D2/GPIO4 -> reset switch

Ausgangsbeschaltung zur Ansteuerung von POWER und RESET:
GPIO mit active HIGH logik
ext. Pulldown-Widerstand -> Basiswiderstand auf NPN-Transistor
Collector ist Schaltausgang und kommt parallel zum jeweiligen Eingang am Mainboard
sollte bei den beiden "safe" GPIOs kein Problem machen

Eingang von Power-LED: 
NPN-Transistor mit Basiswiderstand von POWER_LED, Collector zieht GPIO auf GND wenn LED aktiv